A conventional method of manufacturing semiconductor devices will be described with, reference to FIG. 2, showing the cross sections of a semiconductor device at each manufacturing step. A field oxide film 202 is formed on an element isolation region of a p-type semiconductor substrate 201. A silicon oxide film 203 is formed on the entire surface of the device, and thereafter a first layer polysilicon film 204 is formed. This polysilicon film 204 is formed in order that the silicon oxide film 203 under a gate electrode (to be later formed) not to be contaminated by the resist. Resist is coated on the whole surface of the device, and patterned to form a resist film 230. The structure of the device at this stage is shown in FIG. 2(a).
The polysilicon film 204 and silicon oxide film 203 are etched and patterned using the resist film 230 as a mask, to form polysilicon films 204a and 204b and silicon oxide films 203a and 203b shown in FIG. 2(b). A second layer 206 of polysilicon film 206 is formed on the whole surface of the device, and impurities, such as phosphor ions (P.sup.+), are implanted to form an n-type diffusion region 205 at the area having the thinnest film thickness above the semiconductor substrate 201 and not having the silicon oxide film 203a on the surface thereof.
Resist is coated on the entire surface of the device to form a patterned resist film 211 (FIG. 2(c)). Using the resist film 211 as a mask, the polysilicon film 206, polysilicon films 204a and 204b, and silicon oxide films 203a and 203b are etched. Accordingly, as shown in FIG. 2(c), a gate electrode and a wiring layer are formed at the same time, the gate electrode being formed by the polysilicon films 204aa and 206a on the gate oxide film 203aa, and the wiring layer being formed by the polysilicon films 204b and 206b.
A silicon oxide film 220 is formed on the entire surface of the device, using a thermal oxidization method. Then, phosphor ions (P.sup.+) are implanted as a first-time implantation to form n-type diffusion regions and 222 forming source and drain regions. After forming side walls 223 and 224 on the sides of the gate electrode and wiring layer, phosphor ions (P.sup.+) are implanted as a second-time implantation to form n-type diffusion regions 225 and 226 having a high concentration as shown in FIG. 2(d). The polysilicon film 206b having no underlying silicon film 203b is used for connecting the wiring layer to the n-type diffusion regions 222 and 226 via the n-type diffusion region 205a, and is generally called a buried contact.
The conventional manufacturing method described above, however, has the following associated problems. While etching the polysilicon films 206, 204a and 204b, and silicon oxide films 203a and 203b to form the gate electrode and wiring layer, the surface of the semiconductor substrate 201 without the resist film 211 being covered, is etched to about 1000 angstroms, forming a trench 213 within the n-type diffusion region 205. This phenomenon may cause connection failure between the n-type diffusion region 205 and the n-type diffusion regions 222 and 226, crystal defects, or insufficient insulation because it is difficult to fill an interlayer film between the first and second wiring layers, in the space of the trench 213.
The above-described phenomenon results for the following reasons. First, at the etching step shown in FIG. 2(c), the total film thickness of the gate oxide film 203aa, and polysilicon films 204aa and 206a on the gate electrode is thinner than the film thickness of the polysilicon film 206b at the buried contact area. Second, the insulating silicon oxide film 203 under the buried contact area as an etching stopper has been removed. The n-type diffusion region 205 formed through diffusion of impurities via the polysilicon film 206b into the p-type substrate 201 is electrically connected to the MOSFET n-type diffusion regions 222 and 226 while they are formed, as shown in FIG. 2(d). However, if the size of the trench 213 is large, such electrical connection cannot be realized, resulting in circuit failure.
It is conceivable that the area from which the polysilicon film 206 is removed, is confined to only the area having the silicon oxide film 203a, so as not to form the trench 213. This approach does not provide electrical connection between the n-type diffusion regions 205 and 226 and 222 as shown in FIG. 2(e), also resulting in circuit failure.
In solving the above problems, it is also conceivable that the n-type diffusion region is made large by diffusing phosphor ions (P.sup.+) at a higher concentration at the step shown in FIG. 2(b) into the polysilicon film 204. In this case, however, the n-type diffusion region 205 may extend deeper under the field oxide film 202, lowering the element isolation breakdown voltage.